// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
 * Copyright (C) 2020 frank@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN50IW10_H_
#define _DT_BINDINGS_CLK_SUN50IW10_H_

#define CLK_OSC12M		0
#define CLK_PLL_CPUX		1
#define CLK_PLL_DDR0		2
#define CLK_PLL_PERIPH0		3
#define CLK_PLL_PERIPH0_2X	4
#define CLK_PLL_PERIPH1		5
#define CLK_PLL_PERIPH1_2X	6
#define CLK_PLL_GPU		7
#define CLK_PLL_VIDEO0		8
#define CLK_PLL_VIDEO0_2X	9
#define CLK_PLL_VIDEO0_4X	10
#define CLK_PLL_VIDEO1		11
#define CLK_PLL_VIDEO1_2X	12
#define CLK_PLL_VIDEO1_4X	13
#define CLK_PLL_VIDEO2		14
#define CLK_PLL_VIDEO2_2X	15
#define CLK_PLL_VIDEO2_4X	16
#define CLK_PLL_VIDEO3		17
#define CLK_PLL_VIDEO3_2X	18
#define CLK_PLL_VIDEO3_4X	19
#define CLK_PLL_VE		20
#define CLK_PLL_COM		21
#define CLK_PLL_COM_AUDIO	22
#define CLK_PLL_AUDIO		23
#define CLK_CPUX		24
#define CLK_AXI			25
#define CLK_CPUX_APB		26
#define CLK_PSI_AHB1_AHB2	27
#define CLK_AHB3		28
#define CLK_APB1		29
#define CLK_APB2		30
#define CLK_MBUS		31
#define CLK_DE0			32
#define CLK_DE1			33
#define CLK_BUS_DE0		34
#define CLK_BUS_DE1		35
#define CLK_EINK		36
#define CLK_BUS_EINK		37
#define CLK_G2D			38
#define CLK_BUS_G2D		39
#define CLK_EINK_PANEL		40
#define CLK_GPU			41
#define CLK_BUS_GPU		42
#define CLK_CE			43
#define CLK_BUS_CE		44
#define CLK_VE			45
#define CLK_BUS_VE		46
#define CLK_BUS_DMA		47
#define CLK_BUS_MSGBOX		48
#define CLK_BUS_SPINLOCK	49
#define CLK_BUS_HSTIMER		50
#define CLK_AVS			51
#define CLK_BUS_DBG		52
#define CLK_BUS_PSI		53
#define CLK_BUS_PWM		54
#define CLK_BUS_IOMMU		55
#define CLK_MBUS_DMA		56
#define CLK_MBUS_VE		57
#define CLK_MBUS_CE		58
#define CLK_MBUS_NAND		59
#define CLK_MBUS_CSI		60
#define CLK_MBUS_ISP		61
#define CLK_MBUS_G2D		62
#define CLK_BUS_DRAM		63
#define CLK_NAND0		64
#define CLK_NAND1		65
#define CLK_BUS_NAND		66
#define CLK_MMC0		67
#define CLK_MMC1		68
#define CLK_MMC2		69
#define CLK_MMC3		70
#define CLK_BUS_MMC0		71
#define CLK_BUS_MMC1		72
#define CLK_BUS_MMC2		73
#define CLK_BUS_MMC3		74
#define CLK_BUS_UART0		75
#define CLK_BUS_UART1		76
#define CLK_BUS_UART2		77
#define CLK_BUS_UART3		78
#define CLK_BUS_UART4		79
#define CLK_BUS_UART5		80
#define CLK_BUS_UART6		81
#define CLK_BUS_I2C0		82
#define CLK_BUS_I2C1		83
#define CLK_BUS_I2C2		84
#define CLK_BUS_I2C3		85
#define CLK_BUS_I2C4		86
#define CLK_BUS_I2C5		87
#define CLK_SPI0		88
#define CLK_SPI1		89
#define CLK_SPI2		90
#define CLK_BUS_SPI0		91
#define CLK_BUS_SPI1		92
#define CLK_BUS_SPI2		93
#define CLK_EMAC0_25M		94
#define CLK_EMAC1_25M		95
#define CLK_BUS_EMAC0		96
#define CLK_BUS_EMAC1		97
#define CLK_IR_RX		98
#define CLK_BUS_IR_RX		99
#define CLK_IR_TX		100
#define CLK_BUS_IR_TX		101
#define CLK_BUS_GPADC		102
#define CLK_BUS_THS		103
#define CLK_I2S0		104
#define CLK_I2S1		105
#define CLK_I2S2		106
#define CLK_I2S3		107
#define CLK_BUS_I2S0		108
#define CLK_BUS_I2S1		109
#define CLK_BUS_I2S2		110
#define CLK_BUS_I2S3		111
#define CLK_SPDIF		112
#define CLK_BUS_SPDIF		113
#define CLK_DMIC		114
#define CLK_BUS_DMIC		115
#define CLK_AUDIO_DAC		116
#define CLK_AUDIO_ADC		117
#define CLK_AUDIO_4X		118
#define CLK_BUS_AUDIO_CODEC	119
#define CLK_USB_OHCI0		120
#define CLK_USB_PHY0		121
#define CLK_USB_OHCI1		122
#define CLK_USB_PHY1		123
#define CLK_BUS_OHCI0		124
#define CLK_BUS_OHCI1		125
#define CLK_BUS_EHCI0		126
#define CLK_BUS_EHCI1		127
#define CLK_BUS_OTG		128
#define CLK_BUS_LRADC		129
#define CLK_BUS_DPSS_TOP0	130
#define CLK_BUS_DPSS_TOP1	131
#define CLK_MIPI_DSI		132
#define CLK_BUS_MIPI_DSI	133
#define CLK_TCON_LCD0		134
#define CLK_TCON_LCD1		135
#define CLK_BUS_TCON_LCD0	136
#define CLK_BUS_TCON_LCD1	137
#define CLK_LEDC		138
#define CLK_BUS_LEDC		139
#define CLK_CSI_TOP		140
#define CLK_CSI0_MCLK		141
#define CLK_CSI1_MCLK		142
#define CLK_BUS_CSI		143
#define CLK_CSI_ISP		144

#endif /* _DT_BINDINGS_CLK_SUN50IW10_H_ */
